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PCA9511AD 集成电路 信号缓冲器 中继器
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,PCA9511AD 集成电路 信号缓冲器 中继器

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  • 发 货 期: 7 天内发货
  • 所 在 地: 广东 深圳市 龙岗区
  • 发布日期: 2021年08月12日
深圳市兴华盛电子有限公司进入企业网站查看联系方式
  • 联系人:张 (先生) QQ 3003482651QQ 30034866698
  • 电话:13723468725
  • 传真:075522145608
  • 邮件:eric@tcccoil.com
  • 地址:坂田街道岗头社区新围仔五和大道4010号九层902
型号PCA9511AD厂家NXP
批号20+封装TSSOP-8

接口芯片 接口  信号缓冲器 中继器 分配器 

型号:PCA9511AD  
封装:TSSOP-8


1. General description The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. 2. Features ■ Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems ■ Compatible with I2C-bus Standard-mode, I2C-bus Fast-mode, and SMBus standards ■ Built-in ?V/?t rise time accelerators on all SDA and SCL lines (0.6 V threshold) requires the bus pull-up voltage and supply voltage (VCC) to be the same ■ Active HIGH ENABLE input ■ Active HIGH READY open-drain output ■ High-impedance SDA and SCL pins for VCC =0V ■ 1 V precharge on all SDA and SCL lines ■ Supporting clock stretching and multiple master arbitration/synchronization ■ Operating power supply voltage range: 2.7 V to 5.5 V ■ 0 Hz to 400 kHz clock frequency ■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 ■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ■ Packages offered: SO8, TSSOP8 (MSOP8)


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