The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applicationsrequiring a high level of integration and low power dissipation.The Cortex-M3 is a next generation core that offers better performance than the ARM7 atthe same clock rate and other system enhancements such as modernized debug featuresand a higher level of support BLOCK integration. The Cortex-M3 CPU incorporates a3-stage pipeline and has a Harvard architecture with separate local instruction and databuses, as well as a third bus with slightly lower performance for peripherals. TheCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranches.The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimalperformance when executing code from flash. The LPC178x/7x is targeted to operate atup to 120 MHz CPU frequency.The peripheral complement of the LPC178x/7x includes up to 512 kB of flash programmemory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,External Memory controller (EMC), LCD (LPC178x only), Ethernet, USBDevice/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,three I2C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a QuadratureEncoder Interface, four general purpose timers, two general purpose PWMs with sixoutputs each and one motor control PWM, an ultra-low power RTC with separate batterysupply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allowpin function compatibility with the LPC24xx and LPC23xx.

n Functional replacement for LPC23xx and 24xx family devices.n System:u ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A MemoryProtection Unit (MPU) supporting eight regions is included.u ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).u Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU, and General Purpose DMA controller. Thisinterconnect provides communication with no arbitration delays unless two mastersattempt to access the same slave at the same time.u Split APB bus allows for higher throughput with fewer stalls between the CPU andDMA. A single level of write buffering allows the CPU to continue without waiting forcompletion of APB writes if the APB was not already busy.

u Cortex-M3 system tick timer, including an external clock input option.u Standard JTAG test/debug interface as well as Serial Wire Debug and SerialWireTrace Port options.u Emulation trace module supports real-time trace.u Boundary scan for simplified board testing.u Non-maskable Interrupt (NMI) input.n Memory:u 512 kB on-chip flash program memory with In-System Programming (ISP) andIn-Application Programming (IAP) capabilities. The combination of an enhancedflash memory accelerator and location of the flash memory on the CPU localcode/data bus provides high code performance from flash.u 96 kB on-chip SRAM includes:64 kB of SRAM on the CPU with local code/data bus for high-performance CPUaccess.Two 16 kB SRAM blocks with separate access paths for higher throughput. TheseSRAM blocks may be used for DMA memory as well as for general purposeinstruction and data storage.u 4032 byte on-chip EEPROM.n LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-FilmTransistors (TFT) displays.u Dedicated DMA controller.u Selectable display resolution (up to 1024′ 768 pixels).u Supports up to 24-bit true-color mode.n External Memory Controller (EMC) provides support for asynchronous static memorydevices such as RAM, ROM and flash, as well as dynamic memories such as singLEData rate SDRAM.n Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayermatrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital andDigital-to-Analog converter peripherals, timer match signals, GPIO, and formemory-to-memory transfers.n Serial interfaces:u Ethernet MAC with MII/RMII interface and associated DMA controller. Thesefunctions reside on an independent AHB.u USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY andassociated DMA controller.u Five UARTs with fractional baud rate generation, internal FIFO, DMA support, andRS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and oneUART (USART4) supports IrDA, synchronous mode, and a smart card modeconforming to ISO7816-3.u Three SSP controllers with FIFO and multi-protocol capabilities. The SSPinterfaces can be used with the GPDMA controller.u Three enhanced I2C-bus interfaces, one with a true open-drain output supportingthe full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, twowith standard port pins. Enhancements include multiple address recognition andmonitor mode.u I2S (Inter-IC Sound) interface for digital audio input or output. It can be used withthe GPDMA.

u CAN controller with two channels.n Digital peripherals:u SD/MMC memory card interface.u Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, withconfigurable pull-up/down resistors, open-drain mode, and repeater mode. AllGPIOs are located on an AHB bus for fast access and support Cortex-M3bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Anypin of ports 0 and 2 can be used to generate an interrupt.u Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0and port 2 can be used as edge sensitive interrupt sources.u Four general purpose timers/counters, with a total of eight capture inputs and tencompare outputs. Each timer block has an external count input. Specific timerevents can be selected to generate DMA requests.u Quadrature encoder interface that can monitor one external quadrature encoder.u Two standard PWM/timer blocks with external count input option.u One motor control PWM with support for three-phase motor control.u Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by adedicated RTC oscillator. The RTC block includes 20 bytes of battery-poweredbackup registers, allowing system status to be stored when the rest of the chip ispowered off. Battery power can be supplied from a standard 3 V lithium button cell.The RTC will continue working when the battery voltage drops to as low as 2.1 V.An RTC interrupt can wake up the CPU from any reduced power mode.u Event Recorder that can capture the clock value when an event occurs on any ofthree inputs. The event identification and the time it occurred are stored inregisters. The Event Recorder is located in the RTC power domain and cantherefore operate as long as there is RTC power.u Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internaloscillator, watchdog warning interrupt, and safety features.u CRC Engine block can calculate a CRC on supplied data using one of threestandard polynomials. The CRC engine can be used in conjunction with the DMAcontroller to generate a CRC without CPU involvement in the data transfer.n Analog peripherals:u 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC canbe used with the GPDMA controller.u 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMAsupport.n Power control:u Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down.u The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake upfrom any priority interrupt that can occur while the clocks are stopped inDeep-sleep, Power-down, and Deep power-down modes.u Processor wake-up from Power-down mode via any interrupt able to operateduring Power-down mode (includes external interrupts, RTC interrupt, PORT0/2pin interrupt, and NMI).u Brownout detect with separate threshold for interrupt and forced reset.u On-chip Power-On Reset (POR).

n Clock generation:u Clock output function that can reflect the main oscillator clock, IRC clock, RTCclock, CPU clock, USB clock, or the watchdog timer clock.u On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.u 12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally beused as a system clock.u An on-chip PLL allows CPU operation up to the maximum CPU rate without theneed for a high-frequency crystal. May be run from the main oscillator or theinternal RC oscillator.u A second, dedicated PLL may be used for USB interface in order to allow addedflexibility for the Main PLL settings.n Versatile pin function selection feature allows many possibilities for using on-chipperipheral functions.n Unique device serial number for identification purposes.n Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of-40 °C to 85 °C.n Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package.

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