1.1 FEATURES? Memory configuration ? Three interrupt sources OTP ROM size: 1K * 16 bits. One internal interrupts: T0, TC0. RAM size: 48 * 8 bits. One external interrupts: INT0. Four levels stack buffer ? Two 8-bit Timer/Counter? I/O pin configuration T0: BasIC Timer with 0.5sec RTC. Bi-directional: P0, P1, P2, P5. TC0: Auto-reload timer/Counter/Buzzer output Input only: P1.1. Programmable open-drain: P1.0. ? On chip watchdog timer and clock source is internal Wakeup: P0, P1 level change trigger low clock RC type (16KHz @3V, 32KHz @5V). Pull-up resisters: P0, P1, P2, P5. External Interrupt trigger edge: ? Dual system clocks P0.0 controlLED by PEDGE register. External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz? 3-Level LVD. Internal high clock: 16MHz RC type. Reset system and power monitor. Internal low clock: RC type 16KHz(3V), 32KHz(5V) ? Powerful instructions ? Operating modes One clocks per instruction cycle (1T) Normal mode: Both high and low clock active Most of instructions are one cycle only. Slow mode: Low clock only All ROM area JMP instruction. Sleep mode: Both high and low clock stop All ROM area CALL address instruction. Green mode: Periodical wakeup by T0 Timer All ROM area lookup table function (MOVC) ? Package (Chip form support) PDIP 14 pins SOP 14 pins SSOP 16 pins